1. Field of the Invention
The invention relates to the field of semiconductor processing and more particularly to a MOS integrated circuit in which select transistors are fabricated with a thinner gate oxide than the remaining transistors.
2. Description of the Relevant Art
Very large scale integrated (VLSI) metal-oxide-semiconductor ("MOS") circuits include a large number of interconnected transistors formed in a semiconductor substrate, typically comprised of silicon. Conventionally, the gate electrode of the MOS transistor functions as the transistor's input. The transistor is typically activated or turned on by driving the gate voltage (V.sub.G) to a threshold value referred to as the threshold voltage (V.sub.T). The drain current (I.sub.D) of an MOS transistor typically serves as the transistor's output. Because the gate electrode of each transistor has a small but finite capacitance associated with it, the gate electrode cannot instantaneously achieve a desired change in voltage. Instead, a finite amount of time is required to charge the small gate capacitor to the appropriate voltage level. The amount of time required for a gate electrode to achieve a threshold level can be reduced by decreasing the capacitance of the gate electrode or increasing the drain current of transistors from preceding stages. Generally, for small values of drain voltage, V.sub.D, (i.e., V.sub.D &lt;V.sub.G -V.sub.T), the drain current I.sub.D of an MOS transistor increases linearly with the drain voltage (assuming V.sub.G .gtoreq.V.sub.T). As V.sub.D is increased beyond this linear region, however, I.sub.D levels off and becomes substantially independent of V.sub.D. This value of I.sub.D is commonly referred to as the saturated drain current, I.sub.Dsat. In other words, I.sub.Dsat is the maximum drain current produced by an MOS transistor operating under normal biasing (i.e., V.sub.D .congruent.V.sub.CC, .vertline.V.sub.G .vertline..gtoreq..vertline.V.sub.T .vertline., and V.sub.SS =0 V) for a given gate voltage. I.sub.Dsat is, therefore, a direct measure of the potential speed of an MOS circuit. Increasing I.sub.Dsat increases the integrated circuit's performance by enabling each transistor to drive subsequent stages of transistors to their threshold voltage in less time.
In the linear region, I.sub.D =k(V.sub.G -V.sub.DS /2) V.sub.DS, where k=.mu.C.sub.OX W/L. Inspection of this equation reveals that I.sub.D can be increased by increasing the oxide capacitance C.sub.OX. In addition to increasing k, a larger oxide capacitance reduces the threshold voltages V.sub.T for the general case in which the total charge Q.sub.TOT trapped within the oxide and trapped at the oxide-silicon interface is relatively small. The capacitance, C.sub.OX, of an MOS transistor is closely approximated by that of a parallel plate capacitor such that C.sub.OX .congruent.A.di-elect cons./t.sub.OX, where A is the area of the gate structure, .di-elect cons. is the permitivity of the dielectric, and t.sub.OX is the oxide thickness. Because it is undesirable to increase the area of the gate and difficult to alter the dielectric, increasing the capacitance C.sub.OX must be accomplished by decreasing the oxide thickness t.sub.OX.
In many complementary metal oxide semiconductor (CMOS) processes, the gate structures for the transistors are formed from heavily doped polysilicon. To achieve a degree of symmetry between the p-channel and n-channel transistors, it is not uncommon to dope the gate structures of the n-channel devices with arsenic or phosphorous and the gate structures of the p-channel devices with boron. The doping of the p-channel polysilicon gate with boron can become problematic for thin gate oxide structures due to the relatively rapid rate at which boron diffuses through silicon dioxide.
In very thin oxide structures, (i.e., t.sub.OX .ltoreq.3 nm), boron ions from the heavily doped p+ polysilicon can diffuse through the oxide into the silicon bulk, thereby shifting the threshold voltage V.sub.T of the p-channel devices. This limitation on the thickness of the p-channel oxide has typically limited the oxide thickness of the n-channel devices as well because it is highly desirable from a manufacturing perspective to grow the capacitor or gate oxide non-selectively (i.e., grow the gate across the entire wafer rather than in selected or masked regions of the wafer). The blanket oxide growth tends to result in oxide thicknesses that are uniform across the entire wafer. Furthermore, conventional processing considerations teach away from multiple gate oxide thicknesses within a topography because of the asymmetry that would result from the use of such multiple thickness oxide topographies.
The desire to maintain symmetry has undesirably limited the potential performance of the n-channel devices in certain CMOS processes by restricting the minimum thickness of the gate oxide. More generally, symmetry considerations have prohibited designs in which selected critical transistors could be designated as high-performance, thin-oxide transistors. It would, therefore, be desirable to achieve a semiconductor manufacturing process in which selected transistors incorporate a gate oxide having a first thickness while the remaining transistors have a second gate oxide thickness without unduly complicating the process flow.